As is known, the total dielectric insulation between one or more integrated devices can be obtained by integrating dielectric trenches in substrates of a SOI type in order to form dielectrically insulated wells. These wells are characterized by the presence of a buried-oxide (BOX) layer, which ensures a vertical insulation of the devices, and by the presence of dielectric trenches, which ensure lateral electrical insulation. The continuity between the buried-oxide layer and the dielectric trenches ensures total dielectric insulation of the devices. Furthermore, a field-oxide region delimits the active area where the electronic components are integrated.
FIG. 1 is a schematic representation of the cross-section of a portion 10 of a semiconductor device, comprising a dielectrically insulated well according to the known art. In particular, the portion 10 comprises a bottom region 1, also known as handle-wafer, which normally acts as mechanical support (in case of integration of complex devices, it is sometimes used also as active silicon layer), a buried-oxide (BOX) layer 2, forming a vertical insulation element, and a structural layer 3, of silicon, which, together with the previous layers, forms a silicon-on-insulator (SOI) substrate. An electrical-insulation region 4, of dielectric material, insulates laterally a well 5 and extends up to contact with the oxide layer 2. The surface area of the well 5 is moreover delimited by a field-oxide region 6, which defines the so-called active region or active area of the integrated components within the well 5. The field-oxide region 6 is in contact with the electrical-insulation region 4 and has, in the part inside the well 5, a cusp-like shape referred to, notoriously, as “bird's beak” for the particular conformation derived from the technique used during integration, in this case, the known LOCOS (Local Oxidation of Silicon) technique.
The use of this technique is particularly appreciated in so far as it guarantees that the surface of the entire wafer (and thus also of the well) is sufficiently planar to be able to integrate other layers, either deposited or grown ones, such as, for example, photoresist, nitride, vapox, oxide, metallization layers, etc., necessary for completing integration of the various components. In fact, in the active regions, the silicon-oxide interface is displaced further up with respect to the silicon-oxide interface of the field regions (with thick oxide) by approximately one half of the thickness of the field oxide. This step is almost identical to the surface step that is created between the surface of the thick oxide and the surface of the thin oxide. If the LOCOS technique were not used, any step of non-localized oxidation would entail in fact the presence of a single silicon-oxide interface in a uniform way on the entire surface, and consequently the subsequent etching step for forming the active region, for a same field oxide thickness, would generate a surface step having a thickness practically identical to the thickness of the etched field oxide (and thus in practice with a thickness twice that of the LOCOS structure), causing a poorer planarity of the surface.
From this point of view, the LOCOS technique is advantageous and, notoriously, very diffused, above all in the integration of technologies of the MOS type. Once the LOCOS structure has been defined, the next step is to usually proceed to the integration of the various layers necessary for forming the components. Integration of these layers uses the same LOCOS structure as reference for alignment of the subsequent masks.
Even though, in junction-insulated technologies or partially dielectrically insulated technologies, the formation of the dielectric trench and of the active region is quite consolidated, it should again be noted that, in the case of technologies with total dielectric insulation of the well, the formation of the trenches and of the active region via the LOCOS technique calls for compromises in the process and structure, which, according to the characteristics of the technology to be used, render their integration far from versatile. In particular, with these technologies the insulation well is subjected to mechanical stress due to the presence of the silicon-dielectric interface that surrounds the entire insulation well. The mechanical stress can be caused, for example, by the different expansion coefficient of the dielectric material with respect to silicon in case of thermal cycles or else by the different stoichiometric ratio with which the silicon combines with the various materials that characterize the silicon-dielectric interface in general or also by the local structural conformation that characterizes the silicon-oxide interface. The presence of excessive mechanical stress tends to distort the reticular structure of silicon so that dislocations and, in general, defects tend to form that alter the electrical characteristics of the devices. In particular, the dislocations and alterations of the lattice structure are generated in some critical areas of the insulation well, such as in the silicon region between the electrical-insulation region 4 and the field-oxide region 6, in the silicon region underlying the bird's beak structure, and in the bulk silicon region between the oxide layer 2 and the electrical-insulation region 4.
To overcome the above problems various solutions have been proposed. For example, the hard mask layers necessary for forming the trench on the SOI substrate are used also for forming the active area via LOCOS. This process, however, does not ensure a high performance from the standpoint of defectiveness.
In another approach, lateral dielectric insulation is made at the end of the process sequence, so as to prevent integration of the hard mask necessary for forming the trench being subject to the thermal cycles necessary for the various layers that integrate components within the well. This solution entails a laborious and complex process sequence, with major constraints on the entire structure of the device on account of the selectivity of the materials to be used for the various etching steps, as well as a higher integration cost associated to the laborious industrial-process flow and consequent problems of industrial output.
Still another approach uses integration of MOS devices for low or very low voltages in a SOI wafer with trench insulation, without any versatility in the interchangeability of the process modules and without any teaching as regards the self-alignment of the various layers to the trenches.
There is a need to overcome the drawbacks of the known solutions, providing an integration process in a simplified SOI substrate.